1. Field of the Invention
The present invention relates to a potential detecting circuit and, more particularly, a potential detecting circuit for detecting whether a potential at a predetermined node is higher than a reference potential or not.
2. Description of the Background Art
Conventionally, a dynamic random access memory (hereinbelow, called a DRAM) is provided with a VPP generating circuit for generating a boosted potential VPP higher than an external power supply potential VCC by an amount equal to or higher than a threshold voltage Vthn of an N-channel MOS transistor. The VPP generating circuit is provided with a detector for detecting whether the boosted potential VPP is higher than a target potential or not.
FIG. 15 is a circuit diagram showing the configuration of such a detector 90. In FIG. 15, the detector 90 includes P-channel MOS transistors 91 to 93, N-channel MOS transistors 94 to 98, and inverters 99 to 101. The P-channel MOS transistors 91 and 92 and the N-channel MOS transistors 94 to 96 construct a comparator 102. The P-channel MOS transistors 91 and 92 are connected between a line of the external power supply potential VCC and nodes N91 and N92, respectively. The gates of the P-channel MOS transistors 91 and 92 are connected to the node N91. The P-channel MOS transistors 91 and 92 construct a current mirror circuit. A signal appearing at the node N92 is an output signal xcfx86C of the comparator 102. The N-channel MOS transistor 94 is connected between the node N91 and a node N96, and the N-channel MOS transistor 95 is connected between the node N92 and the node N96. The gates of the N-channel MOS transistors 94 and 95 receive a reference potential VR and a partial potential VD, respectively. The partial potential VD is a potential obtained by dividing the boosted potential VPP at a predetermined voltage dividing rate, and is set to reach the reference potential VR when the boosted potential VPP reaches the target potential. The N-channel MOS transistor 96 is connected between the node N96 and a line of the ground potential GND and its gate receives the external power supply potential VCC. The N-channel MOS transistor 96 serves as a resistive element.
When the partial potential VD is lower than the reference potential VR, a current passing through the MOS transistors 91, 92, and 94 is larger than that passing through the N-channel MOS transistor 95, and the signal xcfx86C is at the xe2x80x9cHxe2x80x9d level (external power supply potential VCC). When the partial potential VD is higher than the reference potential VR, the current passing through the MOS transistors 91, 92, and 94 is smaller than the current passing through the N-channel MOS transistor 95, and the signal xcfx86C is at the xe2x80x9cLxe2x80x9d level (source potential VSC of the N-channel MOS transistors 94 and 95).
The P-channel MOS transistor 93 and the N-channel MOS transistors 97 and 98 construct an inverter 103. The MOS transistors 93, 97, and 98 are connected in series between the line of the external power supply potential VCC and the line of the ground potential GND. Each of the gates of the MOS transistors 93 and 97 receives the signal xcfx86C. A node between the MOS transistors 93 and 97 is an output node N93 of the inverter 103. The gate of the N-channel MOS transistor 98 is connected to the drain of the same transistor. The N-channel MOS transistor 98 serves as a diode. The threshold potential of the inverter 103 is set to an intermediate level between the external power supply potential VCC and the source potential VSC of the N-channel MOS transistors 94 and 95 by the N-channel MOS transistor 98.
When the signal xcfx86C is at the xe2x80x9cHxe2x80x9d level, the P-channel MOS transistor 93 is nonconductive, the N-channel MOS transistor 97 is conductive, and the node N93 is at the xe2x80x9cLxe2x80x9d level (the source potential VSI of the N-channel MOS transistor 97, that is, the threshold potential Vthn of the N-channel MOS transistor 98). When the signal xcfx86C is at the xe2x80x9cLxe2x80x9d level, the N-channel MOS transistor 97 is nonconductive, the P-channel MOS transistor 93 is conductive, and the node N93 is at the xe2x80x9cHxe2x80x9d level (external power supply potential VCC).
A signal appearing at the node N93 is a signal xcfx86EN obtained by being inverted by the inverters 99 to 101. When the signal xcfx86EN is at the xe2x80x9cLxe2x80x9d level, the boosted potential VPP is higher than the target potential. When the signal xcfx86EN is at the xe2x80x9cHxe2x80x9d level, the boosted potential VPP is lower than the target potential. Consequently, by adjusting the boosted potential VPP on the basis of the signal xcfx86EN, the boosted potential VPP can be held at the target potential.
In a semiconductor integrated circuit device such as a DRAM, the size and the power supply voltage of the MOS transistor are being reduced. The reason why the power supply voltage is being reduced is that, as the MOS transistor becomes finer, the withstand voltage of the MOS transistor decreases.
In the detector 90 shown in FIG. 15, however, when the external power supply potential VCC decreases, the speed of response of the detector 90 decreases, and the level regulation of the boosted potential VPP becomes large.
The threshold voltage Vthn of the N-channel MOS transistor has negative temperature dependency. The threshold voltage Vthn decreases at high temperature and increases at low temperature. In order to make the N-channel MOS transistor 97 in the inverter 103 conductive, it is therefore necessary to set the level of the signal xcfx86C to 2xc3x97Vthn or higher. However, since the threshold voltage Vthn increases at low temperature, the operation margin under the condition of a low power supply voltage is slim.
It is therefore an object of the invention to provide a detector capable of assuring an operation margin under the conditions of a low temperature and a low voltage.
In a potential detecting circuit according to the invention, an inverter for outputting an inversion signal of an output signal of a comparator includes: a first transistor of a first conduction type connected between a line of a first power supply potential and an output node, having an input electrode for receiving an output signal of the comparator; a second transistor of a second conduction type having a first electrode connected to the output node and an input electrode for receiving an output signal of the comparator; and a third transistor of the second conduction type connected between a second electrode of the second transistor and a line of a second power supply potential, having an input electrode for receiving a predetermined first potential different from a potential of the second electrode of the second transistor. Therefore, the potential of the second electrode of the second transistor can be set to be lower than a threshold potential of the third transistor. Thus, the operation margin under the conditions of a low voltage and a low temperature is made wider than that in the conventional technique.
Preferably, the comparator includes: fourth and fifth transistors of the first conduction type, the fourth transistor being connected between the line of the first power supply potential and a first node, the fifth transistor being connected between the line of the first power supply potential and a second node, each transistor having an input electrode connected to the first node; sixth and seventh transistors of the second conduction type, the sixth transistor being connected between the first and third nodes and having an input electrode for receiving the reference potential, and the seventh transistor being connected between the second node and the third node and having an input electrode for receiving the potential at the predetermined node; and an eighth transistor of the second conduction type connected between the third node and the line of the second power supply potential, having an input electrode for receiving a predetermined second potential, and the signal of the first or second level is outputted from the second node. In this case, the speed of response of the comparator depends on the second potential.
Preferably, the first potential is the first power supply potential. In this case, the speed of response of the inverter can be set high.
Preferably, the first potential is a constant potential between the first and second power supply potentials. In this case, the dependency of the speed of response of the inverter on the power supply voltage can be reduced.
Preferably, the constant potential is the reference potential. In this case, it is unnecessary to separately generate the first potential, so that the configuration can be simplified.
Preferably, the second potential is the first power supply potential. In this case, the speed of response of the comparator can be set high.
Preferably, the second potential is a constant potential between the first and second power supply potentials. In this case, the dependency of the speed of response of the comparator on the power supply voltage can be reduced.
Preferably, the constant potential is the reference potential. In this case, it is unnecessary to separately generate the second potential, so that the configuration can be simplified.
Preferably, each of the first and second potentials is the reference potential, and the circuit is further provided with: a reference potential generating circuit for generating the reference potential; a first buffer for transmitting the reference potential generated by the reference potential generating circuit to the input electrode in the sixth transistor; and a second buffer for transmitting the reference potential generated by the reference potential generating circuit to the input electrodes in the third and eighth transistors. In this case, it can be prevented that noises occurring in the input electrodes of the third and eighth transistors enter the input electrode of the sixth transistor to thereby cause an erroneous operation in the comparator.
Preferably, each of the first and second potentials is a constant potential between the first and second power supply potentials, and a threshold voltage of each of the second, sixth, and seventh transistors is set to be lower than a threshold voltage of each of the third and eighth transistors. In this case, deterioration in sensitivity of the potential detecting circuit caused by setting the first and second potentials as constant potentials can be prevented.
Preferably, each of the first and second potentials is a constant potential between the first and second power supply potentials, and a threshold voltage of each of the third and eighth transistors is set to be lower than a threshold voltage of each of the second, sixth, and seventh transistors. In this case, reduction in speed of response of the potential detecting circuit caused by setting the first and second potentials as constant potentials can be prevented.
Preferably, an amplifying circuit for amplifying a potential difference between the potential at the predetermined node and the reference potential and applying the resultant potential across the input electrodes of the sixth and seventh transistors is further provided. In this case, even when the potential difference between the first power supply potential and the potential at the predetermined node and that between the first power supply potential and the reference potential are reduced, the comparator operates normally. Thus, the operation margin of the comparator in the lower limit range of the power supply voltage can be widened.
Preferably, a level shifting circuit for level-shifting the potential at the predetermined node to the second power supply potential side and applying the resultant potential to the input electrode of the sixth transistor, and level-shifting the potential at the reference potential to the second power supply potential side and applying the resultant potential to the input electrode of the seventh transistor is further provided. In this case as well, even when the potential difference between the first power supply potential and the potential at the predetermined node and that between the first power supply potential and the reference potential are reduced, the comparator operates normally. Thus, the operation margin of the comparator in the lower limit range of the power supply voltage can be widened.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.